Commercially available integrated circuit memory chips are available with a wide range of access speeds, the access speed being the time required for the memory chip to output selected data from the point in time at which it receives control signals such address information or an enable. Faster memory chips typically cost significantly more than slower memory chips.
One common type of memory chip has a bidirectional data line on which it can both accept and output data, and has a directional control line which, when respectively set to different electrical states, causes the memory component to respectively output onto and accept data from the bidirectional data line. With memory chips of this type, the access time required from the point in time at which an address is presented to the chip until the point in time when the chip outputs valid data traditionally was significantly longer than the access time from a stable signal on the control line to valid data out. In a system, a central processing unit (CPU) typically outputs an address before it provides a control signal to indicate whether the memory chip should output data, and the access time of memory components from address in to data out was sufficiently greater than the access time from control signal in to data out that the latter access time was negligible for purposes of system design.
However, due to advances in technology, the memory component access time from address in to data out has been decreasing relative to the access time from directional control in to data out, and in some cases the former is only a little longer than the latter. Also, CPUs are being designed which are much faster than their recent ancestors. As a result, since as mentioned above the address information is usually provided by the CPU prior to the directional control signal, in certain situations the critical path for propogation delays has become the access time from directional control in to data out rather than the access time from address in to data out. Consequently, it is sometimes necessary to use memory chips which are faster and thus more expensive than would be the case if the critical path for propogation delays depended on the access time from address in to data out.
Accordingly, an object of the present invention is to provide a method and apparatus for controlling a memory component used with a CPU which ensures that the access time from address in to data out rather than the access time from directional control in to data out is the criteria determining the critical path for propogation delays.
A further object is to achieve this result inexpensively, and without the addition of any significant hardware or software.
The objects and purposes of the invention, including those set forth above, are met by providing a method and apparatus in which a high speed memory component has a bidirectional data line and a control line which, when respectively set to first and second electrical states, causes the memory component to respectively output data onto and accept data from the bi-directional data line, and in which an arrangement is provided to initiate transfers of data to and from the memory component on the bidirectional data line and to produce at a first point in time an indication that one of a data read and a data write is being initiated, the control line being set to the second electrical state at a second point in time prior to the first point in time, and the control line being maintained in the second electrical state from the second point in time to the first point in time.
An advantage of the inventive approach is that, when using a very high speed state-of-the-art CPU, it is possible to keep the CPU running at optimum speed by using commercially available memory components, whereas without the inventive approach no commercially available memory component would be fast enough to keep the very high speed CPU running at optimum speed.